1. Field of the Invention
The present invention relates to a semiconductor memory, and more particularly, to a threshold voltage setting circuit for a reference memory cell for immediate and accurate setting of a threshold voltage without time consumption; and a method for setting a threshold voltage using the same.
2. Background of the Related Art
FIG. 1 illustrates a circuitry system of a related art threshold voltage setting circuit for a reference memory cell.
Referring to FIG. 1, the related art threshold voltage setting circuit for a reference memory cell is provided with a plurality of memories 2 each having a gate terminal connected to a wordline 3, and a drain terminal connected to a bitline. There is an inverter connected to an initial input terminal of each wordline 3. There is a selection transistor 5 connected between a cascode device 6 and a drain terminal of respective memories 2 for connection of a column load device 7 to a pertinent memory 2 through the cascode device 6. There is an inverter between a gate terminal and a source terminal of the cascode device 6 for inverting a signal from a source terminal and providing to the gate terminal. There is a plurality of reference memory cell 9 each having a source, a drain, a control gate and a floating gate and connected to a reference column load device 12 through respective selection device 10 and cascode device 11. There is an inverter between the gate terminal and the source terminal of the cascode device 11 for inverting a signal from the source terminal and providing to the gate terminal. And, there is a sense amplifier 8 having an SIN terminal with a voltage level of a contact node CN1 of the column load device 7 and the cascode device 6 applied thereto and a RIN terminal with a voltage level of a contact node CN2 of the column load device 12 and the cascode device 11 applied thereto. There is a switch SW between the contact node CN1 and the SIN for controlling a path for transmitting a signal from the contact node CN1 to the SIN terminal, and there is an NMOS transistor 16 for providing a signal to a pad 15 under the control of the controller 14 when the switch SW is closed. The sense amplifier 8 compares the signal to the SIN terminal to the signal to the RIN terminal. The floating gates of respective reference memory cells 9 are programmed to levels different from one another. In order to program the reference memory cells 9 to different levels, there is a voltage switch 13 for applying charge pulses to the reference memory cells 9 until respective memory cells 9 store target charge amounts. And, there is a controller 14 for controlling the voltage switch 13 the selection device 10, the NMOS transistor and the switch SW. The foregoing related art circuit for setting a threshold voltage for a reference memory cell set the target threshold voltage accurately using a characteristic curve of a load connected to the bitline in the reference memory cell, and provides many program pulse combinations in programming the reference memory cell for minimizing a time period required for programming up to the target threshold voltages. Initially, a program pulse width is made large to permit a threshold voltage shift greater, and the program pulse width is made the smaller gradually as the threshold voltage approaches to a target value the more as the programing is repeated, for securing accuracy to the maximum and minimizing a time period required for reaching to the target threshold voltage. The controller 14 makes the program pulse combinations and sets up a reference for program verification. After programming the reference memory cell, a program verification is made, for verifying reach of the threshold voltage to the target value. And, if not reached to the target, the programming/program verification is repeated until the threshold voltage of the reference memory cell is reached to the target threshold voltage. In other words, in order to initialize more than one reference memory cells having different threshold voltages, accurate verifying reference voltages are applied externally through the controller 14, and a plurality of program pulse combinations are used for reducing an overall program time period.
However, the related art circuit for setting a threshold voltage for a reference memory cell has the following problems.
First, the verification of an injected charge amount required whenever the program pulses are provided to the reference memory cells causes a time period required for reaching to the target threshold voltage longer.
Second, the controller required for using a method, in which, a program pulse width is made large initially and the program pulse width is made the smaller as the threshold voltage approaches to a target value causes the operation complicated.
Third, a resolution for making a final pulse width to approach to a desired target threshold voltage accurately is poor.